Genetic Learning Based Fault Tolerant Cover for Digital Systems

This work proposes a genetic algorithm based technique to learn the structural description of the circuit under study, in order to give it an on line fault tolerant cover. As the circuit operates, its input / output sequences are used to learn the structural configuration of the hardware. Once the structure is evolved, the algorithm redistributes the available redundancy and generates multiple versions of the structure to provide 100% single component fault coverage. The input /output pairs are constantly monitored for possible faults. When a fault is detected, the multiple versions already evolved are made use of to provide fault correction. For a two-dimensional array configuration, it has been found that the number of versions to be evolved ranges from just two to a maximum of the dimensionality of the array. With the number of versions getting reduced because of the redistribution that is done at the learning stage, and the fact that the versions are evolved off-line, the overhead in terms of the system downtime and the number of reconfigurations to be done are minimised. The efficacy of the proposed techniques has been studied using simulations. Hardware implementation has been carried out as a proof of concept. It is found that the proposed fault tolerant cover detects the fault and provides 100% fault correction for single component faults.